Message ID | 1284410994.2007.11.camel@emiko |
---|---|
State | Accepted |
Delegated to: | Leann Ogasawara |
Headers | show |
Applied to Maverick linux master. Thanks, Leann On Mon, 2010-09-13 at 13:49 -0700, Leann Ogasawara wrote: > Hi All, > > The following upstream patch resolves a screen corruption issue after > unplugging an external monitor attached to the VGA port, see LP Bug > 629711. The patch is included in 2.6.36-rc4 and has been Cc'd to > upstream stable. The launchpad bug reporter has also confirmed this > patch resolves the issue. Please consider applying as a pre-stable > patch to Maverick. > > Thanks, > Leann > > From ef69f8c9824106309a1c894bb5fe2a7cea81c4bb Mon Sep 17 00:00:00 2001 > From: Jesse Barnes <jbarnes@virtuousgeek.org> > Date: Thu, 9 Sep 2010 11:58:02 -0700 > Subject: [PATCH] (pre-stable) drm/i915: don't enable self-refresh on Ironlake > > BugLink: http://bugs.launchpad.net/bugs/629711 > > We don't know how to enable it safely, especially as outputs turn on and > off. When disabling LP1 we also need to make sure LP2 and 3 are already > disabled. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29173 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29082 > Reported-by: Chris Lord <chris@linux.intel.com> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > Tested-by: Daniel Vetter <daniel.vetter@ffwll.ch> > Cc: stable@kernel.org > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > (cherry picked from commit dd8849c8f59ec1cee4809a0c5e603e045abe860e) > > Signed-off-by: Leann Ogasawara <leann.ogasawara@canonical.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ > drivers/gpu/drm/i915/intel_display.c | 6 ++++-- > 2 files changed, 12 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index cf41c67..f6dda38 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2199,9 +2199,17 @@ > #define WM1_LP_SR_EN (1<<31) > #define WM1_LP_LATENCY_SHIFT 24 > #define WM1_LP_LATENCY_MASK (0x7f<<24) > +#define WM1_LP_FBC_LP1_MASK (0xf<<20) > +#define WM1_LP_FBC_LP1_SHIFT 20 > #define WM1_LP_SR_MASK (0x1ff<<8) > #define WM1_LP_SR_SHIFT 8 > #define WM1_LP_CURSOR_MASK (0x3f) > +#define WM2_LP_ILK 0x4510c > +#define WM2_LP_EN (1<<31) > +#define WM3_LP_ILK 0x45110 > +#define WM3_LP_EN (1<<31) > +#define WM1S_LP_ILK 0x45120 > +#define WM1S_LP_EN (1<<31) > > /* Memory latency timer register */ > #define MLTR_ILK 0x11222 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 48ad60b..9a00dc4 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3176,8 +3176,7 @@ static void ironlake_update_wm(struct drm_device *dev, int planea_clock, > reg_value = I915_READ(WM1_LP_ILK); > reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK | > WM1_LP_CURSOR_MASK); > - reg_value |= WM1_LP_SR_EN | > - (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) | > + reg_value |= (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) | > (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm; > > I915_WRITE(WM1_LP_ILK, reg_value); > @@ -5395,6 +5394,9 @@ void intel_init_clock_gating(struct drm_device *dev) > I915_WRITE(DISP_ARB_CTL, > (I915_READ(DISP_ARB_CTL) | > DISP_FBC_WM_DIS)); > + I915_WRITE(WM3_LP_ILK, 0); > + I915_WRITE(WM2_LP_ILK, 0); > + I915_WRITE(WM1_LP_ILK, 0); > } > return; > } else if (IS_G4X(dev)) { > -- > 1.7.1 > > > >
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cf41c67..f6dda38 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2199,9 +2199,17 @@ #define WM1_LP_SR_EN (1<<31) #define WM1_LP_LATENCY_SHIFT 24 #define WM1_LP_LATENCY_MASK (0x7f<<24) +#define WM1_LP_FBC_LP1_MASK (0xf<<20) +#define WM1_LP_FBC_LP1_SHIFT 20 #define WM1_LP_SR_MASK (0x1ff<<8) #define WM1_LP_SR_SHIFT 8 #define WM1_LP_CURSOR_MASK (0x3f) +#define WM2_LP_ILK 0x4510c +#define WM2_LP_EN (1<<31) +#define WM3_LP_ILK 0x45110 +#define WM3_LP_EN (1<<31) +#define WM1S_LP_ILK 0x45120 +#define WM1S_LP_EN (1<<31) /* Memory latency timer register */ #define MLTR_ILK 0x11222 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 48ad60b..9a00dc4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3176,8 +3176,7 @@ static void ironlake_update_wm(struct drm_device *dev, int planea_clock, reg_value = I915_READ(WM1_LP_ILK); reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK | WM1_LP_CURSOR_MASK); - reg_value |= WM1_LP_SR_EN | - (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) | + reg_value |= (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) | (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm; I915_WRITE(WM1_LP_ILK, reg_value); @@ -5395,6 +5394,9 @@ void intel_init_clock_gating(struct drm_device *dev) I915_WRITE(DISP_ARB_CTL, (I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS)); + I915_WRITE(WM3_LP_ILK, 0); + I915_WRITE(WM2_LP_ILK, 0); + I915_WRITE(WM1_LP_ILK, 0); } return; } else if (IS_G4X(dev)) {