@@ -3955,7 +3955,7 @@
shl\t%<rtn>0<vas>, %<rtn>1<vas>, %2
ushl\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas>"
[(set_attr "simd" "no,no,yes,yes")
- (set_attr "type" "bfm,shift_reg,neon_shift_imm<q>, neon_shift_reg<q>")]
+ (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>, neon_shift_reg<q>")]
)
;; Logical right shift using SISD or Integer instruction
@@ -3972,7 +3972,7 @@
#
#"
[(set_attr "simd" "no,no,yes,yes,yes")
- (set_attr "type" "bfm,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
+ (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
)
(define_split
@@ -4019,7 +4019,7 @@
#
#"
[(set_attr "simd" "no,no,yes,yes,yes")
- (set_attr "type" "bfm,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
+ (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
)
(define_split
@@ -4129,7 +4129,7 @@
"@
<shift>\\t%w0, %w1, %2
<shift>\\t%w0, %w1, %w2"
- [(set_attr "type" "bfm,shift_reg")]
+ [(set_attr "type" "bfx,shift_reg")]
)
(define_insn "*<optab><mode>3_insn"
@@ -4141,7 +4141,7 @@
operands[3] = GEN_INT (<sizen> - UINTVAL (operands[2]));
return "<bfshift>\t%w0, %w1, %2, %3";
}
- [(set_attr "type" "bfm")]
+ [(set_attr "type" "bfx")]
)
(define_insn "*extr<mode>5_insn"
@@ -4234,7 +4234,7 @@
operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
- [(set_attr "type" "bfm")]
+ [(set_attr "type" "bfx")]
)
(define_insn "*zero_extend<GPI:mode>_lshr<SHORT:mode>"
@@ -4247,7 +4247,7 @@
operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
return "ubfx\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
- [(set_attr "type" "bfm")]
+ [(set_attr "type" "bfx")]
)
(define_insn "*extend<GPI:mode>_ashr<SHORT:mode>"
@@ -4260,7 +4260,7 @@
operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
return "sbfx\\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
- [(set_attr "type" "bfm")]
+ [(set_attr "type" "bfx")]
)
;; -------------------------------------------------------------------
@@ -4283,7 +4283,7 @@
(match_operand 3 "const_int_operand" "n")))]
""
"<su>bfx\\t%<w>0, %<w>1, %3, %2"
- [(set_attr "type" "bfm")]
+ [(set_attr "type" "bfx")]
)
;; Bitfield Insert (insv)
@@ -4365,7 +4365,7 @@
: GEN_INT (<GPI:sizen> - UINTVAL (operands[2]));
return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
- [(set_attr "type" "bfm")]
+ [(set_attr "type" "bfx")]
)
;; XXX We should match (any_extend (ashift)) here, like (and (ashift)) below
@@ -4377,7 +4377,7 @@
(match_operand 3 "const_int_operand" "n")))]
"aarch64_mask_and_shift_for_ubfiz_p (<MODE>mode, operands[3], operands[2])"
"ubfiz\\t%<w>0, %<w>1, %2, %P3"
- [(set_attr "type" "bfm")]
+ [(set_attr "type" "bfx")]
)
(define_insn "bswap<mode>2"
@@ -39,7 +39,7 @@
(define_insn_reservation "thunderx_shift" 1
(and (eq_attr "tune" "thunderx")
- (eq_attr "type" "bfm,extend,rotate_imm,shift_imm,shift_reg,rbit,rev"))
+ (eq_attr "type" "bfm,bfx,extend,rotate_imm,shift_imm,shift_reg,rbit,rev"))
"thunderx_pipe0 | thunderx_pipe1")
@@ -93,7 +93,7 @@
(and (eq_attr "tune" "cortexa53")
(eq_attr "type" "alu_shift_imm,alus_shift_imm,
crc,logic_shift_imm,logics_shift_imm,
- alu_ext,alus_ext,bfm,extend,mvn_shift"))
+ alu_ext,alus_ext,bfm,bfx,extend,mvn_shift"))
"cortex_a53_slot_any")
(define_insn_reservation "cortex_a53_alu_shift_reg" 3
@@ -297,7 +297,7 @@
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
- adr,bfm,clz,csel,rbit,rev,alu_dsp_reg,\
+ adr,bfm,bfx,clz,rbit,rev,alu_dsp_reg,\
rotate_imm,shift_imm,shift_reg,\
mov_imm,mov_reg,\
mvn_imm,mvn_reg,\
@@ -358,7 +358,7 @@
(eq_attr "type" "alu_imm, alus_imm, logic_imm, logics_imm,\
alu_sreg, alus_sreg, logic_reg, logics_reg,\
adc_imm, adcs_imm, adc_reg, adcs_reg,\
- adr, bfm, clz, rbit, rev, csel, alu_dsp_reg,\
+ adr, bfm, bfx, clz, rbit, rev, csel, alu_dsp_reg,\
shift_imm, shift_reg, rotate_imm, extend,\
mov_imm, mov_reg,\
mvn_imm, mvn_reg,\
@@ -372,7 +372,7 @@
(eq_attr "type" "alu_imm, alus_imm, logic_imm, logics_imm,\
alu_sreg, alus_sreg, logic_reg, logics_reg,\
adc_imm, adcs_imm, adc_reg, adcs_reg,\
- adr, bfm, clz, rbit, rev, alu_dsp_reg,\
+ adr, bfm, bfx, clz, rbit, rev, alu_dsp_reg,\
shift_imm, shift_reg, rotate_imm, extend,\
mov_imm, mov_reg,\
mvn_imm, mvn_reg,\
@@ -51,6 +51,7 @@
; alus_shift_imm as alu_shift_imm, setting condition flags.
; alus_shift_reg as alu_shift_reg, setting condition flags.
; bfm bitfield move operation.
+; bfx bitfield extract operation.
; block blockage insn, this blocks all functional units.
; branch branch.
; call subroutine call.
@@ -557,6 +558,7 @@
alus_shift_imm,\
alus_shift_reg,\
bfm,\
+ bfx,\
block,\
branch,\
call,\
@@ -164,7 +164,7 @@
(define_insn_reservation "xgene1_bfm" 2
(and (eq_attr "tune" "xgene1")
- (eq_attr "type" "bfm"))
+ (eq_attr "type" "bfm,bfx"))
"xgene1_decode1op,xgene1_fsu")
(define_insn_reservation "xgene1_f_rint" 5