===================================================================
@@ -53,6 +53,353 @@
#define __CR6_LT 2
#define __CR6_LT_REV 3
+/* Machinery to support overloaded functions in C. */
+#include "overload.h"
+
+/* Overloaded function declarations. Please maintain these in
+ alphabetical order. */
+
+/* Since __builtin_choose_expr and __builtin_types_compatible_p
+ aren't permitted in C++, we'll need to use standard overloading
+ for those. Disable this mechanism for C++. GNU extensions are
+ also unavailable for -ansi, -std=c11, etc. */
+#ifndef __STRICT_ANSI__
+#ifndef __cplusplus
+
+#ifdef __POWER8_VECTOR__
+#define vec_add(a1, a2) \
+ OVERLOAD_2ARG_28VAR(vec_add, a1, a2, \
+ 1, vector bool char, vector signed char, \
+ 2, vector signed char, vector bool char, \
+ 3, vector signed char, vector signed char, \
+ 4, vector bool char, vector unsigned char, \
+ 5, vector unsigned char, vector bool char, \
+ 6, vector unsigned char, vector unsigned char, \
+ 7, vector bool short, vector signed short, \
+ 8, vector signed short, vector bool short, \
+ 9, vector signed short, vector signed short, \
+ 10, vector bool short, vector unsigned short, \
+ 11, vector unsigned short, vector bool short, \
+ 12, vector unsigned short, vector unsigned short, \
+ 13, vector bool int, vector signed int, \
+ 14, vector signed int, vector bool int, \
+ 15, vector signed int, vector signed int, \
+ 16, vector bool int, vector unsigned int, \
+ 17, vector unsigned int, vector bool int, \
+ 18, vector unsigned int, vector unsigned int, \
+ 19, vector bool long long, vector signed long long, \
+ 20, vector signed long long, vector bool long long, \
+ 21, vector signed long long, vector signed long long, \
+ 22, vector bool long long, vector unsigned long long, \
+ 23, vector unsigned long long, vector bool long long, \
+ 24, vector unsigned long long, vector unsigned long long, \
+ 25, vector float, vector float, \
+ 26, vector double, vector double, \
+ 27, vector signed __int128, vector signed __int128, \
+ 28, vector unsigned __int128, vector unsigned __int128)
+#elif defined __VSX__
+#define vec_add(a1, a2) \
+ OVERLOAD_2ARG_28VAR(vec_add, a1, a2, \
+ 1, vector bool char, vector signed char, \
+ 2, vector signed char, vector bool char, \
+ 3, vector signed char, vector signed char, \
+ 4, vector bool char, vector unsigned char, \
+ 5, vector unsigned char, vector bool char, \
+ 6, vector unsigned char, vector unsigned char, \
+ 7, vector bool short, vector signed short, \
+ 8, vector signed short, vector bool short, \
+ 9, vector signed short, vector signed short, \
+ 10, vector bool short, vector unsigned short, \
+ 11, vector unsigned short, vector bool short, \
+ 12, vector unsigned short, vector unsigned short, \
+ 13, vector bool int, vector signed int, \
+ 14, vector signed int, vector bool int, \
+ 15, vector signed int, vector signed int, \
+ 16, vector bool int, vector unsigned int, \
+ 17, vector unsigned int, vector bool int, \
+ 18, vector unsigned int, vector unsigned int, \
+ 19, vector bool long long, vector signed long long, \
+ 20, vector signed long long, vector bool long long, \
+ 21, vector signed long long, vector signed long long, \
+ 22, vector bool long long, vector unsigned long long, \
+ 23, vector unsigned long long, vector bool long long, \
+ 24, vector unsigned long long, vector unsigned long long, \
+ 25, vector float, vector float, \
+ 26, vector double, vector double, \
+ 26, vector double, vector double, \
+ 26, vector double, vector double)
+#else
+#define vec_add(a1, a2) \
+ OVERLOAD_2ARG_28VAR(vec_add, a1, a2, \
+ 1, vector bool char, vector signed char, \
+ 2, vector signed char, vector bool char, \
+ 3, vector signed char, vector signed char, \
+ 4, vector bool char, vector unsigned char, \
+ 5, vector unsigned char, vector bool char, \
+ 6, vector unsigned char, vector unsigned char, \
+ 7, vector bool short, vector signed short, \
+ 8, vector signed short, vector bool short, \
+ 9, vector signed short, vector signed short, \
+ 10, vector bool short, vector unsigned short, \
+ 11, vector unsigned short, vector bool short, \
+ 12, vector unsigned short, vector unsigned short, \
+ 13, vector bool int, vector signed int, \
+ 14, vector signed int, vector bool int, \
+ 15, vector signed int, vector signed int, \
+ 16, vector bool int, vector unsigned int, \
+ 17, vector unsigned int, vector bool int, \
+ 18, vector unsigned int, vector unsigned int, \
+ 18, vector unsigned int, vector unsigned int, \
+ 18, vector unsigned int, vector unsigned int, \
+ 18, vector unsigned int, vector unsigned int, \
+ 18, vector unsigned int, vector unsigned int, \
+ 18, vector unsigned int, vector unsigned int, \
+ 18, vector unsigned int, vector unsigned int, \
+ 25, vector float, vector float, \
+ 25, vector float, vector float, \
+ 25, vector float, vector float, \
+ 25, vector float, vector float)
+#endif /* __POWER8_VECTOR__ #elif __VSX__ */
+
+#endif /* !__cplusplus */
+
+OVERLOAD_2ARG_DECL(vec_add, 1, \
+ vector signed char, \
+ vector bool char, a1, \
+ vector signed char, a2)
+{
+ return (vector signed char)a1 + a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 2, \
+ vector signed char, \
+ vector signed char, a1, \
+ vector bool char, a2)
+{
+ return a1 + (vector signed char)a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 3, \
+ vector signed char, \
+ vector signed char, a1, \
+ vector signed char, a2)
+{
+ return a1 + a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 4, \
+ vector unsigned char, \
+ vector bool char, a1, \
+ vector unsigned char, a2)
+{
+ return (vector unsigned char)a1 + a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 5, \
+ vector unsigned char, \
+ vector unsigned char, a1, \
+ vector bool char, a2)
+{
+ return a1 + (vector unsigned char)a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 6, \
+ vector unsigned char, \
+ vector unsigned char, a1, \
+ vector unsigned char, a2)
+{
+ return a1 + a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 7, \
+ vector signed short, \
+ vector bool short, a1, \
+ vector signed short, a2)
+{
+ return (vector signed short)a1 + a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 8, \
+ vector signed short, \
+ vector signed short, a1, \
+ vector bool short, a2)
+{
+ return a1 + (vector signed short)a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 9, \
+ vector signed short, \
+ vector signed short, a1, \
+ vector signed short, a2)
+{
+ return a1 + a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 10, \
+ vector unsigned short, \
+ vector bool short, a1, \
+ vector unsigned short, a2)
+{
+ return (vector unsigned short)a1 + a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 11, \
+ vector unsigned short, \
+ vector unsigned short, a1, \
+ vector bool short, a2)
+{
+ return a1 + (vector unsigned short)a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 12, \
+ vector unsigned short, \
+ vector unsigned short, a1, \
+ vector unsigned short, a2)
+{
+ return a1 + a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 13, \
+ vector signed int, \
+ vector bool int, a1, \
+ vector signed int, a2)
+{
+ return (vector signed int)a1 + a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 14, \
+ vector signed int, \
+ vector signed int, a1, \
+ vector bool int, a2)
+{
+ return a1 + (vector signed int)a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 15, \
+ vector signed int, \
+ vector signed int, a1, \
+ vector signed int, a2)
+{
+ return a1 + a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 16, \
+ vector unsigned int, \
+ vector bool int, a1, \
+ vector unsigned int, a2)
+{
+ return (vector unsigned int)a1 + a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 17, \
+ vector unsigned int, \
+ vector unsigned int, a1, \
+ vector bool int, a2)
+{
+ return a1 + (vector unsigned int)a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 18, \
+ vector unsigned int, \
+ vector unsigned int, a1, \
+ vector unsigned int, a2)
+{
+ return a1 + a2;
+}
+
+#ifdef __VSX__
+OVERLOAD_2ARG_DECL(vec_add, 19, \
+ vector signed long long, \
+ vector bool long long, a1, \
+ vector signed long long, a2)
+{
+ return (vector signed long long)a1 + a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 20, \
+ vector signed long long, \
+ vector signed long long, a1, \
+ vector bool long long, a2)
+{
+ return a1 + (vector signed long long)a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 21, \
+ vector signed long long, \
+ vector signed long long, a1, \
+ vector signed long long, a2)
+{
+ return a1 + a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 22, \
+ vector unsigned long long, \
+ vector bool long long, a1, \
+ vector unsigned long long, a2)
+{
+ return (vector unsigned long long)a1 + a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 23, \
+ vector unsigned long long, \
+ vector unsigned long long, a1, \
+ vector bool long long, a2)
+{
+ return a1 + (vector unsigned long long)a2;
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 24, \
+ vector unsigned long long, \
+ vector unsigned long long, a1, \
+ vector unsigned long long, a2)
+{
+ return a1 + a2;
+}
+#endif /* __VSX__ */
+
+OVERLOAD_2ARG_DECL(vec_add, 25, \
+ vector float, \
+ vector float, a1, \
+ vector float, a2)
+{
+ return a1 + a2;
+}
+
+#ifdef __VSX__
+OVERLOAD_2ARG_DECL(vec_add, 26, \
+ vector double, \
+ vector double, a1, \
+ vector double, a2)
+{
+ return a1 + a2;
+}
+#endif /* __VSX__ */
+
+/* Currently we do not early-expand vec_add for vector __int128. This
+ is because vector lowering in the middle end casts V1TImode to TImode,
+ which is probably appropriate since we have very little support for
+ V1TImode arithmetic. Late expansion ensures we get the single
+ instruction add. */
+#ifdef __POWER8_VECTOR__
+OVERLOAD_2ARG_DECL(vec_add, 27, \
+ vector signed __int128, \
+ vector signed __int128, a1, \
+ vector signed __int128, a2)
+{
+ return __builtin_vec_add (a1, a2);
+}
+
+OVERLOAD_2ARG_DECL(vec_add, 28, \
+ vector unsigned __int128, \
+ vector unsigned __int128, a1, \
+ vector unsigned __int128, a2)
+{
+ return __builtin_vec_add (a1, a2);
+}
+#endif /* __POWER8_VECTOR__ */
+
+#endif /* !__STRICT_ANSI__ */
+
/* Synonyms. */
#define vec_vaddcuw vec_addc
#define vec_vand vec_and
@@ -190,7 +537,9 @@
#define vec_vupklsb __builtin_vec_vupklsb
#define vec_abs __builtin_vec_abs
#define vec_abss __builtin_vec_abss
+#ifdef __STRICT_ANSI__
#define vec_add __builtin_vec_add
+#endif
#define vec_adds __builtin_vec_adds
#define vec_and __builtin_vec_and
#define vec_andc __builtin_vec_andc
===================================================================
@@ -0,0 +1,206 @@
+/* Overloaded Built-In Function Support
+ Copyright (C) 2016 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef _OVERLOAD_H
+#define _OVERLOAD_H 1
+
+/* Since __builtin_choose_expr and __builtin_types_compatible_p
+ aren't permitted in C++, we'll need to use standard overloading
+ for those. Disable this mechanism for C++. GNU extensions are
+ also unavailable for -ansi, -std=c11, etc. */
+#if !defined __cplusplus && !defined __STRICT_ANSI__
+
+/* Macros named OVERLOAD_<N>ARG_<M>VAR provide a dispatch mechanism
+ for built-in functions taking N input arguments and M overloaded
+ variants. Note that indentation conventions for nested calls to
+ __builtin_choose_expr are violated for practicality. Please
+ maintain these macros in increasing order by N and M for ease
+ of reuse. */
+
+#define OVERLOAD_2ARG_28VAR(NAME, ARG1, ARG2, \
+ VAR1_ID, VAR1_TYPE1, VAR1_TYPE2, \
+ VAR2_ID, VAR2_TYPE1, VAR2_TYPE2, \
+ VAR3_ID, VAR3_TYPE1, VAR3_TYPE2, \
+ VAR4_ID, VAR4_TYPE1, VAR4_TYPE2, \
+ VAR5_ID, VAR5_TYPE1, VAR5_TYPE2, \
+ VAR6_ID, VAR6_TYPE1, VAR6_TYPE2, \
+ VAR7_ID, VAR7_TYPE1, VAR7_TYPE2, \
+ VAR8_ID, VAR8_TYPE1, VAR8_TYPE2, \
+ VAR9_ID, VAR9_TYPE1, VAR9_TYPE2, \
+ VAR10_ID, VAR10_TYPE1, VAR10_TYPE2, \
+ VAR11_ID, VAR11_TYPE1, VAR11_TYPE2, \
+ VAR12_ID, VAR12_TYPE1, VAR12_TYPE2, \
+ VAR13_ID, VAR13_TYPE1, VAR13_TYPE2, \
+ VAR14_ID, VAR14_TYPE1, VAR14_TYPE2, \
+ VAR15_ID, VAR15_TYPE1, VAR15_TYPE2, \
+ VAR16_ID, VAR16_TYPE1, VAR16_TYPE2, \
+ VAR17_ID, VAR17_TYPE1, VAR17_TYPE2, \
+ VAR18_ID, VAR18_TYPE1, VAR18_TYPE2, \
+ VAR19_ID, VAR19_TYPE1, VAR19_TYPE2, \
+ VAR20_ID, VAR20_TYPE1, VAR20_TYPE2, \
+ VAR21_ID, VAR21_TYPE1, VAR21_TYPE2, \
+ VAR22_ID, VAR22_TYPE1, VAR22_TYPE2, \
+ VAR23_ID, VAR23_TYPE1, VAR23_TYPE2, \
+ VAR24_ID, VAR24_TYPE1, VAR24_TYPE2, \
+ VAR25_ID, VAR25_TYPE1, VAR25_TYPE2, \
+ VAR26_ID, VAR26_TYPE1, VAR26_TYPE2, \
+ VAR27_ID, VAR27_TYPE1, VAR27_TYPE2, \
+ VAR28_ID, VAR28_TYPE1, VAR28_TYPE2) \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR1_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR1_TYPE2), \
+ _##NAME##_##VAR1_ID ((VAR1_TYPE1)ARG1, (VAR1_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR2_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR2_TYPE2), \
+ _##NAME##_##VAR2_ID ((VAR2_TYPE1)ARG1, (VAR2_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR3_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR3_TYPE2), \
+ _##NAME##_##VAR3_ID ((VAR3_TYPE1)ARG1, (VAR3_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR4_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR4_TYPE2), \
+ _##NAME##_##VAR4_ID ((VAR4_TYPE1)ARG1, (VAR4_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR5_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR5_TYPE2), \
+ _##NAME##_##VAR5_ID ((VAR5_TYPE1)ARG1, (VAR5_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR6_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR6_TYPE2), \
+ _##NAME##_##VAR6_ID ((VAR6_TYPE1)ARG1, (VAR6_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR7_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR7_TYPE2), \
+ _##NAME##_##VAR7_ID ((VAR7_TYPE1)ARG1, (VAR7_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR8_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR8_TYPE2), \
+ _##NAME##_##VAR8_ID ((VAR8_TYPE1)ARG1, (VAR8_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR9_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR9_TYPE2), \
+ _##NAME##_##VAR9_ID ((VAR9_TYPE1)ARG1, (VAR9_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR10_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR10_TYPE2), \
+ _##NAME##_##VAR10_ID ((VAR10_TYPE1)ARG1, (VAR10_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR11_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR11_TYPE2), \
+ _##NAME##_##VAR11_ID ((VAR11_TYPE1)ARG1, (VAR11_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR12_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR12_TYPE2), \
+ _##NAME##_##VAR12_ID ((VAR12_TYPE1)ARG1, (VAR12_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR13_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR13_TYPE2), \
+ _##NAME##_##VAR13_ID ((VAR13_TYPE1)ARG1, (VAR13_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR14_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR14_TYPE2), \
+ _##NAME##_##VAR14_ID ((VAR14_TYPE1)ARG1, (VAR14_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR15_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR15_TYPE2), \
+ _##NAME##_##VAR15_ID ((VAR15_TYPE1)ARG1, (VAR15_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR16_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR16_TYPE2), \
+ _##NAME##_##VAR16_ID ((VAR16_TYPE1)ARG1, (VAR16_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR17_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR17_TYPE2), \
+ _##NAME##_##VAR17_ID ((VAR17_TYPE1)ARG1, (VAR17_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR18_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR18_TYPE2), \
+ _##NAME##_##VAR18_ID ((VAR18_TYPE1)ARG1, (VAR18_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR19_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR19_TYPE2), \
+ _##NAME##_##VAR19_ID ((VAR19_TYPE1)ARG1, (VAR19_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR20_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR20_TYPE2), \
+ _##NAME##_##VAR20_ID ((VAR20_TYPE1)ARG1, (VAR20_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR21_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR21_TYPE2), \
+ _##NAME##_##VAR21_ID ((VAR21_TYPE1)ARG1, (VAR21_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR22_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR22_TYPE2), \
+ _##NAME##_##VAR22_ID ((VAR22_TYPE1)ARG1, (VAR22_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR23_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR23_TYPE2), \
+ _##NAME##_##VAR23_ID ((VAR23_TYPE1)ARG1, (VAR23_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR24_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR24_TYPE2), \
+ _##NAME##_##VAR24_ID ((VAR24_TYPE1)ARG1, (VAR24_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR25_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR25_TYPE2), \
+ _##NAME##_##VAR25_ID ((VAR25_TYPE1)ARG1, (VAR25_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR26_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR26_TYPE2), \
+ _##NAME##_##VAR26_ID ((VAR26_TYPE1)ARG1, (VAR26_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR27_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR27_TYPE2), \
+ _##NAME##_##VAR27_ID ((VAR27_TYPE1)ARG1, (VAR27_TYPE2)ARG2), \
+ __builtin_choose_expr ( \
+ __builtin_types_compatible_p (__typeof__ (ARG1), VAR28_TYPE1) \
+ && __builtin_types_compatible_p (__typeof__ (ARG2), VAR28_TYPE2), \
+ _##NAME##_##VAR28_ID ((VAR28_TYPE1)ARG1, (VAR28_TYPE2)ARG2), \
+ (void)0))))))))))))))))))))))))))))
+
+/* Macros named OVERLOAD_<N>ARG_DECL provide a declaration for one
+ variant of an overloaded built-in function having N arguments.
+ Please maintain these macros in increasing order by N for ease
+ of reuse. */
+
+#define OVERLOAD_2ARG_DECL(NAME, VAR_ID, TYPE0, \
+ TYPE1, ARG1, \
+ TYPE2, ARG2) \
+static __inline__ TYPE0 __attribute__ ((__always_inline__)) \
+_##NAME##_##VAR_ID (TYPE1 ARG1, TYPE2 ARG2)
+
+/* With C++, we can just use function overloading. */
+#elif defined __cplusplus && !defined __STRICT_ANSI__
+
+#define OVERLOAD_2ARG_DECL(NAME, VAR_ID, TYPE0, \
+ TYPE1, ARG1, \
+ TYPE2, ARG2) \
+static __inline__ TYPE0 __attribute__ ((__always_inline__)) \
+NAME (TYPE1 ARG1, TYPE2 ARG2)
+
+#endif /* !__cplusplus && !__STRICT_ANSI__ */
+
+#endif /* _OVERLOAD_H */
===================================================================
@@ -440,7 +440,7 @@ nvptx-*-*)
;;
powerpc*-*-*)
cpu_type=rs6000
- extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h htmintrin.h htmxlintrin.h"
+ extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h htmintrin.h htmxlintrin.h overload.h"
case x$with_cpu in
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
cpu_is_64bit=yes
@@ -2279,13 +2279,13 @@ powerpc-*-darwin*)
;;
esac
tmake_file="${tmake_file} t-slibgcc"
- extra_headers=altivec.h
+ extra_headers="altivec.h overload.h"
;;
powerpc64-*-darwin*)
extra_options="${extra_options} ${cpu_type}/darwin.opt"
tmake_file="${tmake_file} ${cpu_type}/t-darwin64 t-slibgcc"
tm_file="${tm_file} ${cpu_type}/darwin8.h ${cpu_type}/darwin64.h"
- extra_headers=altivec.h
+ extra_headers="altivec.h overload.h"
;;
powerpc*-*-freebsd*)
tm_file="${tm_file} dbxelf.h elfos.h ${fbsd_tm_file} rs6000/sysv4.h"
@@ -2512,7 +2512,7 @@ rs6000-ibm-aix5.3.* | powerpc-ibm-aix5.3.*)
use_collect2=yes
thread_file='aix'
use_gcc_stdint=wrap
- extra_headers=altivec.h
+ extra_headers="altivec.h overload.h"
;;
rs6000-ibm-aix6.* | powerpc-ibm-aix6.*)
tm_file="${tm_file} rs6000/aix.h rs6000/aix61.h rs6000/xcoff.h rs6000/aix-stdint.h"
@@ -2521,7 +2521,7 @@ rs6000-ibm-aix6.* | powerpc-ibm-aix6.*)
use_collect2=yes
thread_file='aix'
use_gcc_stdint=wrap
- extra_headers=altivec.h
+ extra_headers="altivec.h overload.h"
default_use_cxa_atexit=yes
;;
rs6000-ibm-aix[789].* | powerpc-ibm-aix[789].*)
@@ -2531,7 +2531,7 @@ rs6000-ibm-aix[789].* | powerpc-ibm-aix[789].*)
use_collect2=yes
thread_file='aix'
use_gcc_stdint=wrap
- extra_headers=altivec.h
+ extra_headers="altivec.h overload.h"
default_use_cxa_atexit=yes
;;
rl78-*-elf*)
===================================================================
@@ -0,0 +1,46 @@
+/* Verify that overloaded built-ins for vec_add with char
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-additional-options "-std=gnu11" } */
+
+#include <altivec.h>
+
+vector signed char
+test1 (vector bool char x, vector signed char y)
+{
+ return vec_add (x, y);
+}
+
+vector signed char
+test2 (vector signed char x, vector bool char y)
+{
+ return vec_add (x, y);
+}
+
+vector signed char
+test3 (vector signed char x, vector signed char y)
+{
+ return vec_add (x, y);
+}
+
+vector unsigned char
+test4 (vector bool char x, vector unsigned char y)
+{
+ return vec_add (x, y);
+}
+
+vector unsigned char
+test5 (vector unsigned char x, vector bool char y)
+{
+ return vec_add (x, y);
+}
+
+vector unsigned char
+test6 (vector unsigned char x, vector unsigned char y)
+{
+ return vec_add (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vaddubm" 6 } } */
===================================================================
@@ -0,0 +1,46 @@
+/* Verify that overloaded built-ins for vec_add with short
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-additional-options "-std=gnu11" } */
+
+#include <altivec.h>
+
+vector signed short
+test1 (vector bool short x, vector signed short y)
+{
+ return vec_add (x, y);
+}
+
+vector signed short
+test2 (vector signed short x, vector bool short y)
+{
+ return vec_add (x, y);
+}
+
+vector signed short
+test3 (vector signed short x, vector signed short y)
+{
+ return vec_add (x, y);
+}
+
+vector unsigned short
+test4 (vector bool short x, vector unsigned short y)
+{
+ return vec_add (x, y);
+}
+
+vector unsigned short
+test5 (vector unsigned short x, vector bool short y)
+{
+ return vec_add (x, y);
+}
+
+vector unsigned short
+test6 (vector unsigned short x, vector unsigned short y)
+{
+ return vec_add (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vadduhm" 6 } } */
===================================================================
@@ -0,0 +1,46 @@
+/* Verify that overloaded built-ins for vec_add with int
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-additional-options "-std=gnu11" } */
+
+#include <altivec.h>
+
+vector signed int
+test1 (vector bool int x, vector signed int y)
+{
+ return vec_add (x, y);
+}
+
+vector signed int
+test2 (vector signed int x, vector bool int y)
+{
+ return vec_add (x, y);
+}
+
+vector signed int
+test3 (vector signed int x, vector signed int y)
+{
+ return vec_add (x, y);
+}
+
+vector unsigned int
+test4 (vector bool int x, vector unsigned int y)
+{
+ return vec_add (x, y);
+}
+
+vector unsigned int
+test5 (vector unsigned int x, vector bool int y)
+{
+ return vec_add (x, y);
+}
+
+vector unsigned int
+test6 (vector unsigned int x, vector unsigned int y)
+{
+ return vec_add (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vadduwm" 6 } } */
===================================================================
@@ -0,0 +1,46 @@
+/* Verify that overloaded built-ins for vec_add with long long
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-additional-options "-std=gnu11" } */
+
+#include <altivec.h>
+
+vector signed long long
+test1 (vector bool long long x, vector signed long long y)
+{
+ return vec_add (x, y);
+}
+
+vector signed long long
+test2 (vector signed long long x, vector bool long long y)
+{
+ return vec_add (x, y);
+}
+
+vector signed long long
+test3 (vector signed long long x, vector signed long long y)
+{
+ return vec_add (x, y);
+}
+
+vector unsigned long long
+test4 (vector bool long long x, vector unsigned long long y)
+{
+ return vec_add (x, y);
+}
+
+vector unsigned long long
+test5 (vector unsigned long long x, vector bool long long y)
+{
+ return vec_add (x, y);
+}
+
+vector unsigned long long
+test6 (vector unsigned long long x, vector unsigned long long y)
+{
+ return vec_add (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vaddudm" 6 } } */
===================================================================
@@ -0,0 +1,16 @@
+/* Verify that overloaded built-ins for vec_add with float
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-additional-options "-std=gnu11 -mno-vsx" } */
+
+#include <altivec.h>
+
+vector float
+test1 (vector float x, vector float y)
+{
+ return vec_add (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vaddfp" 1 } } */
===================================================================
@@ -0,0 +1,23 @@
+/* Verify that overloaded built-ins for vec_add with float and
+ double inputs for VSX produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-additional-options "-std=gnu11" } */
+
+#include <altivec.h>
+
+vector float
+test1 (vector float x, vector float y)
+{
+ return vec_add (x, y);
+}
+
+vector double
+test2 (vector double x, vector double y)
+{
+ return vec_add (x, y);
+}
+
+/* { dg-final { scan-assembler-times "xvaddsp" 1 } } */
+/* { dg-final { scan-assembler-times "xvadddp" 1 } } */
===================================================================
@@ -0,0 +1,22 @@
+/* Verify that overloaded built-ins for vec_add with __int128
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-additional-options "-std=gnu11 -Wno-pedantic" } */
+
+#include "altivec.h"
+
+vector signed __int128
+test1 (vector signed __int128 x, vector signed __int128 y)
+{
+ return vec_add (x, y);
+}
+
+vector unsigned __int128
+test2 (vector unsigned __int128 x, vector unsigned __int128 y)
+{
+ return vec_add (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vadduqm" 2 } } */