| Message ID | 1470129653-15854-5-git-send-email-yangbo.lu@nxp.com |
|---|---|
| State | Changes Requested |
| Delegated to: | York Sun |
| Headers | show |
Hi York, I have a question about CONFIG option. Are we going to completely using Kconfig in the future like kernel? I just found below compiling error. =============Error log=================== ./scripts/check-config.sh u-boot.cfg \ ./scripts/config_whitelist.txt . 1>&2 Error: You must add new CONFIG options using Kconfig The following new ad-hoc CONFIG options were detected: CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 Please add these via Kconfig instead. Find a suitable Kconfig file and add a 'config' or 'menuconfig' option. make: *** [all] Error 1 =========================================== As you know, all CONFIG options of the QorIQ eSDHC driver were defined in <board>.h. Should we convert to use Kconfig for eSDHC driver? Thanks. Best regards, Yangbo Lu > -----Original Message----- > From: Yangbo Lu [mailto:yangbo.lu@nxp.com] > Sent: Tuesday, August 02, 2016 5:21 PM > To: u-boot@lists.denx.de > Cc: york sun; Jaehoon Chung; Yangbo Lu > Subject: [v2, 5/5] arch/arm, arch/powerpc: enable workaround for eSDHC > erratum A009620 > > This patch is to enable workaround for eSDHC erratum A009620. All the > affected platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ > T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A). > > Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> > --- > Changes for v2: > - Added this patch > - Moved definition out of board files > --- > arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++ > arch/arm/include/asm/arch-ls102xa/config.h | 1 + > arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ > 3 files changed, 11 insertions(+) > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h > b/arch/arm/include/asm/arch-fsl-layerscape/config.h > index b0ad4b4..7f31fcd 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h > @@ -32,6 +32,7 @@ > #define CONFIG_NUM_DDR_CONTROLLERS 3 > #define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */ > #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 > #define SRDS_MAX_LANES 8 > #define CONFIG_SYS_FSL_SRDS_1 > #define CONFIG_SYS_FSL_SRDS_2 > @@ -175,6 +176,7 @@ > #define CONFIG_SYS_NUM_FM1_DTSEC 7 > #define CONFIG_SYS_NUM_FM1_10GEC 1 > #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 > #define CONFIG_SYS_FSL_DDR_BE > #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) > #define CONFIG_MAX_MEM_MAPPED > CONFIG_SYS_DDR_BLOCK1_SIZE > diff --git a/arch/arm/include/asm/arch-ls102xa/config.h > b/arch/arm/include/asm/arch-ls102xa/config.h > index d408fe4..054f05d 100644 > --- a/arch/arm/include/asm/arch-ls102xa/config.h > +++ b/arch/arm/include/asm/arch-ls102xa/config.h > @@ -131,6 +131,7 @@ > #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 > #define CONFIG_SYS_FSL_ERRATUM_A008378 > #define CONFIG_SYS_FSL_ERRATUM_A009663 > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 > #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 > #else > #error SoC not defined > diff --git a/arch/powerpc/include/asm/config_mpc85xx.h > b/arch/powerpc/include/asm/config_mpc85xx.h > index 505d355..b3d8fe8 100644 > --- a/arch/powerpc/include/asm/config_mpc85xx.h > +++ b/arch/powerpc/include/asm/config_mpc85xx.h > @@ -148,6 +148,7 @@ > #define CONFIG_TSECV2 > #define CONFIG_SYS_FSL_SEC_COMPAT 4 > #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 > #define CONFIG_NUM_DDR_CONTROLLERS 1 > #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 > #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 > @@ -369,6 +370,7 @@ > #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 > #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define > CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 > #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 > #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 > #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 > @@ -530,6 +532,7 @@ > #define CONFIG_SYS_FSL_USB2_PHY_ENABLE > #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY > #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 > #define CONFIG_SYS_FSL_ERRATUM_USB14 > #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define > CONFIG_SYS_FSL_ERRATUM_DDR_A003474 > @@ -568,6 +571,7 @@ > #define CONFIG_SYS_FSL_USB2_PHY_ENABLE > #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY > #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 > #define CONFIG_SYS_FSL_ERRATUM_USB14 > #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define > CONFIG_SYS_FSL_ERRATUM_DDR_A003474 > @@ -686,6 +690,7 @@ > #define CONFIG_SYS_FSL_ERRATUM_A007186 > #define CONFIG_SYS_FSL_ERRATUM_A006593 > #define CONFIG_SYS_FSL_ERRATUM_A007798 > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 > #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 > #define CONFIG_SYS_FSL_SFP_VER_3_0 > #define CONFIG_SYS_FSL_PCI_VER_3_X > @@ -802,6 +807,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) > #define CONFIG_SYS_FSL_ERRATUM_A006261 > #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 > #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 > #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE > #define QE_MURAM_SIZE 0x6000UL > #define MAX_QE_RISC 1 > @@ -823,6 +829,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) > #endif #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) > #define CONFIG_MAX_CPUS 2 > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 > #elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) > #define CONFIG_MAX_CPUS 1 > #endif > @@ -882,6 +889,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) > #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 > #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 > #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 > #elif defined(CONFIG_PPC_T2081) > #define CONFIG_SYS_NUM_FM1_DTSEC 6 > #define CONFIG_SYS_NUM_FM1_10GEC 2 > -- > 2.1.0.27.g96db324
On 10/18/2016 02:39 AM, Y.B. Lu wrote: > Hi York, > > I have a question about CONFIG option. Are we going to completely using Kconfig in the future like kernel? > I just found below compiling error. > > =============Error log=================== > ./scripts/check-config.sh u-boot.cfg \ > ./scripts/config_whitelist.txt . 1>&2 > Error: You must add new CONFIG options using Kconfig > The following new ad-hoc CONFIG options were detected: > CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 > > Please add these via Kconfig instead. Find a suitable Kconfig > file and add a 'config' or 'menuconfig' option. > make: *** [all] Error 1 > =========================================== > > As you know, all CONFIG options of the QorIQ eSDHC driver were defined in <board>.h. > Should we convert to use Kconfig for eSDHC driver? > That is the direction U-Boot is taking. Please check my recent commits on upstream U-Boot for examples to move config macros to Kconfig. I converted some DDR options, and some errata macros. York
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index b0ad4b4..7f31fcd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -32,6 +32,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 3 #define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */ #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define SRDS_MAX_LANES 8 #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 @@ -175,6 +176,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 7 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index d408fe4..054f05d 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -131,6 +131,7 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_ERRATUM_A008378 #define CONFIG_SYS_FSL_ERRATUM_A009663 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else #error SoC not defined diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 505d355..b3d8fe8 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -148,6 +148,7 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 @@ -369,6 +370,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -530,6 +532,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define CONFIG_SYS_FSL_ERRATUM_USB14 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 @@ -568,6 +571,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define CONFIG_SYS_FSL_ERRATUM_USB14 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 @@ -686,6 +690,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_FSL_ERRATUM_A007798 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_PCI_VER_3_X @@ -802,6 +807,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -823,6 +829,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #endif #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) #define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_MAX_CPUS 1 #endif @@ -882,6 +889,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #elif defined(CONFIG_PPC_T2081) #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2
This patch is to enable workaround for eSDHC erratum A009620. All the affected platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A). Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> --- Changes for v2: - Added this patch - Moved definition out of board files --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++ arch/arm/include/asm/arch-ls102xa/config.h | 1 + arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ 3 files changed, 11 insertions(+)