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nvlink: Present chip ID as the NPU PHB slot location

Message ID 20160616012441.13118-1-ruscur@russell.cc
State Accepted
Headers show

Commit Message

Russell Currey June 16, 2016, 1:24 a.m. UTC 
EEH errors in the kernel report the physical slot location of the
erroneous PE and its PHB.  For NPU devices, the PE's slot location will
refer to the physical GPU the link is associated with, and the PHB is
actually a NPU chip which has no relevance to a physical slot on a board.

Rather than reporting N/A for a NPU PHB's slot location, present the chip
number.  It's not particularly useful, but better than nothing.

Signed-off-by: Russell Currey <ruscur@russell.cc>
---
 hw/npu.c | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Stewart Smith June 21, 2016, 5:57 a.m. UTC | #1 
Russell Currey <ruscur@russell.cc> writes:
> EEH errors in the kernel report the physical slot location of the
> erroneous PE and its PHB.  For NPU devices, the PE's slot location will
> refer to the physical GPU the link is associated with, and the PHB is
> actually a NPU chip which has no relevance to a physical slot on a board.
>
> Rather than reporting N/A for a NPU PHB's slot location, present the chip
> number.  It's not particularly useful, but better than nothing.
>
> Signed-off-by: Russell Currey <ruscur@russell.cc>
> ---
>  hw/npu.c | 8 ++++++++
>  1 file changed, 8 insertions(+)

Looks good, merged to master as of 0f23e5b
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Patch

diff --git a/hw/npu.c b/hw/npu.c
index c371f4c..b99a2e5 100644
--- a/hw/npu.c
+++ b/hw/npu.c
@@ -1710,6 +1710,7 @@  static void npu_add_phb_properties(struct npu *p)
 			   0x800, 0x0, 0x0, 0x1, icsp, base_lsi + 2,
 			   0x800, 0x0, 0x0, 0x2, icsp, base_lsi + 3 };
 	uint32_t mask[] = {0xf800, 0x0, 0x0, 0x7};
+	char slotbuf[32];
 
 	/* Add various properties that HB doesn't have to
 	 * add, some of them simply because they result from
@@ -1764,6 +1765,13 @@  static void npu_add_phb_properties(struct npu *p)
 			      hi32(mm_base), lo32(mm_base),
 			      hi32(mm_base), lo32(mm_base),
 			      hi32(mm_size), lo32(mm_size));
+
+	/* Set the slot location on the NPU PHB.  This PHB can contain
+	 * devices that correlate with multiple physical slots, so
+	 * present the chip ID instead.
+	 */
+	snprintf(slotbuf, sizeof(slotbuf), "NPU Chip %d", p->chip_id);
+	dt_add_property_string(np, "ibm,io-base-loc-code", slotbuf);
 }
 
 static void npu_create_phb(struct dt_node *dn)