[ARM] : rewrite NEON bitwise operations without UNSPECs

This patch is another installment in the series I started with this one (which 
is still awaiting review)

http://gcc.gnu.org/ml/gcc-patches/2010-05/msg02262.html

which is aimed at using canonical RTL where possible to express NEON 
instructions rather than UNSPECs.  For many of the NEON intructions we've 
already had an UNSPEC version for use by the intrinsics in addition to a regular 
RTL version, so merging them is good for simplifying the back end.  See my 
comments in the first patch for more discussion since most of it applies here as 
well.

This installment adds canonical RTL for the NEON bitwise operations.  I have one 
more piece in the series for arithmetic operations, and two related patches (one 
that addresses a DImode performance problem introduced by this series, and one 
that fixes the IEEE conformance issue reported in PR43703 that partly overlaps 
the arithmetic patch).  I'll be posting these patches shortly as well.

The new piece of functionality in this patch is support for DImode operations 
using NEON instructions instead of doing the operations piecewise using SImode 
chunks.  We had some problems with performance tuning of this approach. 
Basically, the issue is that there is a very high cost of transferring operands 
back and forth between the NEON registers and the core registers.  If we have a 
series of DImode operations chained together, we should therefore use the same 
register class for all of them, but GCC doesn't seem to have a way to express 
this kind of constraint.  The approach taken here is to uniformly disparage the 
core-register alternatives for DImode operations, on the theory that (a) 
preferring to use NEON registers when possible will reduce pressure on the core 
registers and (b) in cases where operands have to be put in core registers to 
satisfy constraints on other instructions, that should trickle down so that we 
can still use the disparaged alternatives.

These changes have been in our local tree for a while and I last tested this 
version of the patch against mainline head a few weeks ago, using an 
arm-none-eabi build with simulator testing for both NEON and non-NEON 
compilation options.  OK to check in?

-Sandra

2010-06-21  Sandra Loosemore  <sandra@codesourcery.com>

	gcc/
	* config/arm/neon.md (UNSPEC_VAND): Delete.
	(UNSPEC_VBIC): Delete.
	(UNSPEC_VCLZ): Delete.
	(UNSPEC_VCNT): Delete.
	(UNSPEC_VEOR): Delete.
	(UNSPEC_VORN): Delete.
	(UNSPEC_VORR): Delete.
	(iordi3_neon): Rewrite RTL without unspec.  Add alternatives to handle
	core registers too.
	(anddi3_neon): Likewise.
	(orndi3_neon): Likewise.
	(bicdi3_neon): Likewise.
	(xordi3_neon): Likewise.
	(neon_vclz<mode>): Rewrite as define_expand and clz<mode>2 to get
	rid of unspec and handle unused operand.
	(neon_vcnt<mode>): Similarly, with popcount<mode>2.
	* config/arm/predicates.md (imm_for_neon_logic_operand):
	Require TARGET_NEON.
	(imm_for_neon_inv_logic_operand): Likewise.
	* config/arm/arm.md (define_split for logical_binary_operator):
	Disable for NEON registers.
	(anddi3): Add new define_expand, and rename the insn.  Disable
	this insn for NEON, where anddi3_neon now applies.
	(*anddi_notdi_di): Disable for TARGET_NEON, where bicdi3_neon applies.
	(iordi3): As for anddi3.
	(xordi3): Likewise.
	* config/arm/neon.ml (Vand): Split DImode variants and mark them
	as No_op to disable testing for exact instruction match.
	(Vorr): Likewise.
	(Veor): Likewise.
	(Vbic): Likewise.
	(Vorn): Likewise.
	* config/arm/arm_neon.h: Regenerated.
	* doc/arm-neon-intrinsics.texi: Regenerated.

	gcc/testsuite/
	* gcc.target/arm/neon-vands64.c: New.
	* gcc.target/arm/neon-vandu64.c: New.
	* gcc.target/arm/neon-vbics64.c: New.
	* gcc.target/arm/neon-vbicu64.c: New.
	* gcc.target/arm/neon-veors64.c: New.
	* gcc.target/arm/neon-veoru64.c: New.
	* gcc.target/arm/neon-vorns64.c: New.
	* gcc.target/arm/neon-vornu64.c: New.
	* gcc.target/arm/neon-vorrs64.c: New.
	* gcc.target/arm/neon-vorru64.c: New.
	* gcc.target/arm/neon/vands64.c: Regenerated.
	* gcc.target/arm/neon/vandu64.c: Regenerated.
	* gcc.target/arm/neon/vbics64.c: Regenerated.
	* gcc.target/arm/neon/vbicu64.c: Regenerated.
	* gcc.target/arm/neon/veors64.c: Regenerated.
	* gcc.target/arm/neon/veoru64.c: Regenerated.
	* gcc.target/arm/neon/vorns64.c: Regenerated.
	* gcc.target/arm/neon/vornu64.c: Regenerated.
	* gcc.target/arm/neon/vorrs64.c: Regenerated.
	* gcc.target/arm/neon/vorru64.c: Regenerated.

[ARM] : rewrite NEON bitwise operations without UNSPECs

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