Message ID | B5E67142681B53468FAF6B7C313565624F4EBEC2@hhmail02.hh.imgtec.org |
---|---|
State | New |
Headers | show |
Robert Suchanek <Robert.Suchanek@imgtec.com> writes: > A small patch to correct the latency for M5100. > > Ok to commit? > * config/mips/m5100.md (m51_int_load): Update the latency to 2. OK. Matthew
> > Ok to commit? > > > * config/mips/m5100.md (m51_int_load): Update the latency to 2. > > OK. Committed - r236288 Robert
diff --git a/gcc/config/mips/m5100.md b/gcc/config/mips/m5100.md index f69fc7f..8d87b70 100644 --- a/gcc/config/mips/m5100.md +++ b/gcc/config/mips/m5100.md @@ -65,7 +65,7 @@ (define_insn_reservation "m51_int_jump" 1 ;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs ;; prefetch: prefetch, prefetchx -(define_insn_reservation "m51_int_load" 3 +(define_insn_reservation "m51_int_load" 2 (and (eq_attr "cpu" "m5100") (eq_attr "type" "load,prefetch,prefetchx")) "m51_alu")