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[v2,2/6] disas/mips: Add R6 jr/jr.hb to disassembler

Message ID 1443697130-21431-3-git-send-email-james.hogan@imgtec.com
State New
Headers show

Commit Message

James Hogan Oct. 1, 2015, 10:58 a.m. UTC 
MIPS r6 encodes jr as jalr zero, and jr.hb as jalr.hb zero, so add these
encodings to the MIPS disassembly table.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Leon Alrae <leon.alrae@imgtec.com>
---
 disas/mips.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Richard Henderson Oct. 1, 2015, 7:42 p.m. UTC | #1 
On 10/01/2015 08:58 PM, James Hogan wrote:
> MIPS r6 encodes jr as jalr zero, and jr.hb as jalr.hb zero, so add these
> encodings to the MIPS disassembly table.
>
> Signed-off-by: James Hogan<james.hogan@imgtec.com>
> Cc: Aurelien Jarno<aurelien@aurel32.net>
> Cc: Leon Alrae<leon.alrae@imgtec.com>
> ---
>   disas/mips.c | 2 ++
>   1 file changed, 2 insertions(+)

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~
Leon Alrae Oct. 2, 2015, 9:19 a.m. UTC | #2 
On 01/10/15 11:58, James Hogan wrote:
> @@ -2420,9 +2420,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
>  {"hibernate","",        0x42000023, 0xffffffff,	0, 			0,		V1	},
>  {"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,    		0,		I33	},
>  {"jr",      "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,		0,		I1	},
> +{"jr",      "s",	0x00000009, 0xfc1fffff,	UBD|RD_s,		0,		I32R6	}, /* jalr */
>  /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
>     the same hazard barrier effect.  */
>  {"jr.hb",   "s",	0x00000408, 0xfc1fffff,	UBD|RD_s,		0,		I32	},
> +{"jr.hb",   "s",	0x00000408, 0xfc1fffff,	UBD|RD_s,		0,		I32R6	}, /* jalr.hb */

jr.hb match should be 0x00000409, otherwise:

Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
James Hogan Oct. 2, 2015, 9:22 a.m. UTC | #3 
On Fri, Oct 02, 2015 at 10:19:11AM +0100, Leon Alrae wrote:
> On 01/10/15 11:58, James Hogan wrote:
> > @@ -2420,9 +2420,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
> >  {"hibernate","",        0x42000023, 0xffffffff,	0, 			0,		V1	},
> >  {"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,    		0,		I33	},
> >  {"jr",      "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,		0,		I1	},
> > +{"jr",      "s",	0x00000009, 0xfc1fffff,	UBD|RD_s,		0,		I32R6	}, /* jalr */
> >  /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
> >     the same hazard barrier effect.  */
> >  {"jr.hb",   "s",	0x00000408, 0xfc1fffff,	UBD|RD_s,		0,		I32	},
> > +{"jr.hb",   "s",	0x00000408, 0xfc1fffff,	UBD|RD_s,		0,		I32R6	}, /* jalr.hb */
> 
> jr.hb match should be 0x00000409, otherwise:
> 
> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
> 

Whoops, well spotted, thanks Leon!

Cheers
James
diff mbox

Patch

diff --git a/disas/mips.c b/disas/mips.c
index 01336a83852d..2a24014f2cae 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -2420,9 +2420,11 @@  const struct mips_opcode mips_builtin_opcodes[] =
 {"hibernate","",        0x42000023, 0xffffffff,	0, 			0,		V1	},
 {"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,    		0,		I33	},
 {"jr",      "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,		0,		I1	},
+{"jr",      "s",	0x00000009, 0xfc1fffff,	UBD|RD_s,		0,		I32R6	}, /* jalr */
 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
    the same hazard barrier effect.  */
 {"jr.hb",   "s",	0x00000408, 0xfc1fffff,	UBD|RD_s,		0,		I32	},
+{"jr.hb",   "s",	0x00000408, 0xfc1fffff,	UBD|RD_s,		0,		I32R6	}, /* jalr.hb */
 {"j",       "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,		0,		I1	}, /* jr */
 /* SVR4 PIC code requires special handling for j, so it must be a
    macro.  */