Message ID | 1430263075-27682-7-git-send-email-ashcharles@gmail.com |
---|---|
State | Deferred |
Delegated to: | Tom Rini |
Headers | show |
On Tue, Apr 28, 2015 at 04:17:55PM -0700, Ash Charles wrote: > From: Arun Bharadwaj <arun@gumstix.com> > > Overo boards with board revision 0 use a 256MB RAM + 256MB NAND chip. > For an unknown reason, these boards fail to boot a 3.17.8 kernel based > on the RAM size configuration in u-boot. As a workaround, fake out the > RAM setting in u-boot (discussion [1]). > > [1] http://gumstix.8.x6.nabble.com/running-built-images-tt4969794.html > > Signed-off-by: Arun Bharadwaj <arun@gumstix.com> > Signed-off-by: Ash Charles <ashcharles@gmail.com> Just for the record (since I just dug into it), this change was included in the v2 of the series that created board/overo/spl.c and thus not needed.
Ah---good catch. Thanks for the explanation Tom. --Ash On Sun, May 10, 2015 at 7:07 AM, Tom Rini <trini@konsulko.com> wrote: > On Tue, Apr 28, 2015 at 04:17:55PM -0700, Ash Charles wrote: > >> From: Arun Bharadwaj <arun@gumstix.com> >> >> Overo boards with board revision 0 use a 256MB RAM + 256MB NAND chip. >> For an unknown reason, these boards fail to boot a 3.17.8 kernel based >> on the RAM size configuration in u-boot. As a workaround, fake out the >> RAM setting in u-boot (discussion [1]). >> >> [1] http://gumstix.8.x6.nabble.com/running-built-images-tt4969794.html >> >> Signed-off-by: Arun Bharadwaj <arun@gumstix.com> >> Signed-off-by: Ash Charles <ashcharles@gmail.com> > > Just for the record (since I just dug into it), this change was included > in the v2 of the series that created board/overo/spl.c and thus not > needed. > > -- > Tom
diff --git a/board/overo/spl.c b/board/overo/spl.c index 64c33d6..e1652c3 100644 --- a/board/overo/spl.c +++ b/board/overo/spl.c @@ -59,7 +59,7 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) timings->mr = MICRON_V_MR_165; switch (get_board_revision()) { case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ - timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->mcfg = MICRON_V_MCFG_165(256 << 20); timings->ctrla = MICRON_V_ACTIMA_165; timings->ctrlb = MICRON_V_ACTIMB_165; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;