| Message ID | 553E8654.6000103@gmail.com |
|---|---|
| State | Not Applicable |
| Headers | show |
Am 27.04.2015 um 20:56 schrieb Heiner Kallweit: > The only other difference I found is the initial setting of LED_CTRL3 register. > Could you please test the following patch (first remove the initial patch attempt)? [ 0.850000] switch0: Atheros AR833X rev. 2 switch registered on ag71xx-mdio.0 [ 0.860000] Atheros AR8216/AR8236/AR8316 ag71xx-mdio.0:00: led_val = 3f [ 0.860000] Atheros AR8216/AR8236/AR8316 ag71xx-mdio.0:00: Detected AR8337 It seems that we have no luck here... In case you have any new idea I'll test the patch. Here is a picture of the switch chip: http://c33.imgup.net/2015-04-166a5b.jpg Best Christian
On Tue, Apr 28, 2015 at 5:15 AM, Christian Mehlis <christian@m3hlis.de> wrote: > Am 27.04.2015 um 20:56 schrieb Heiner Kallweit: >> >> The only other difference I found is the initial setting of LED_CTRL3 >> register. >> Could you please test the following patch (first remove the initial patch >> attempt)? > > > [ 0.850000] switch0: Atheros AR833X rev. 2 switch registered on > ag71xx-mdio.0 > [ 0.860000] Atheros AR8216/AR8236/AR8316 ag71xx-mdio.0:00: led_val = 3f > [ 0.860000] Atheros AR8216/AR8236/AR8316 ag71xx-mdio.0:00: Detected > AR8337 > > It seems that we have no luck here... > In case you have any new idea I'll test the patch. Here's some general info about the QCA8334 chip that might help. If you have specific questions let me know and I will try to find answers. The four ports of the Gigabit switch engine are: Port 0 GMAC: RGMII/MII/RMII Port 2 and 3 GMAC: 2 *10/100/1000BASE-T Port 6 GMAC: SerDes/SGMII It can be configured using serial EEPROM and/or the MDC/MDIO interface. kg
Am 28.04.2015 um 14:15 schrieb Christian Mehlis: > Am 27.04.2015 um 20:56 schrieb Heiner Kallweit: >> The only other difference I found is the initial setting of LED_CTRL3 register. >> Could you please test the following patch (first remove the initial patch attempt)? > > [ 0.850000] switch0: Atheros AR833X rev. 2 switch registered on ag71xx-mdio.0 > [ 0.860000] Atheros AR8216/AR8236/AR8316 ag71xx-mdio.0:00: led_val = 3f > [ 0.860000] Atheros AR8216/AR8236/AR8316 ag71xx-mdio.0:00: Detected AR8337 > > It seems that we have no luck here... > In case you have any new idea I'll test the patch. > > Here is a picture of the switch chip: > http://c33.imgup.net/2015-04-166a5b.jpg > > Best > Christian > . > I found a datasheet for QCA8334 and according to it these bits in LED_CTRl3 are supposed to be 0 for this chip. But this doesn't seem to be true .. Meanwhile I'm running out of ideas how to tell between the two chips. However I have another hypothesis: The drivers sets bit MAC06_EXCHANGE_EN for AR8337. According to the datasheet this means "Exchange MAC0 and MAC6". My assumption is that MAC6 is used as CPU port if this bit is set. Having said this whether to set this bit or not might not be chip-specific but board-specific (CPU connected to MAC0 vs. MAC6 pins of the switch chip). AR8334 has no MAC6 (R)GMII pins therefore this bit must not be set. Not sure how many supported devices actually use an AR8337. Maybe they share some reference design and use MAC6 in general? Conclusion would be that the driver can not know whether to set the bit or not. It would have to be defined in platform configuration or device tree. I'm not an expert and refactored few parts of the driver only. Therefore I can not promise any quick results, however I'll have a look at it. Rgds, Heiner
diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.h b/target/linux/generic/files/drivers/net/phy/ar8216.h index 0f53f23..a23c3be 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8216.h +++ b/target/linux/generic/files/drivers/net/phy/ar8216.h @@ -405,6 +405,7 @@ struct ar8xxx_priv { struct mutex reg_mutex; u8 chip_ver; u8 chip_rev; + u8 chip_subver; const struct ar8xxx_chip *chip; void *chip_data; bool initialized; @@ -562,11 +563,21 @@ static inline bool chip_is_ar8327(struct ar8xxx_priv *priv) return priv->chip_ver == AR8XXX_VER_AR8327; } -static inline bool chip_is_ar8337(struct ar8xxx_priv *priv) +static inline bool chip_is_ar833x(struct ar8xxx_priv *priv) { return priv->chip_ver == AR8XXX_VER_AR8337; } +static inline bool chip_is_ar8334(struct ar8xxx_priv *priv) +{ + return chip_is_ar833x(priv) && priv->chip_subver == 4; +} + +static inline bool chip_is_ar8337(struct ar8xxx_priv *priv) +{ + return chip_is_ar833x(priv) && priv->chip_subver == 7; +} + static inline void ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val) { diff --git a/target/linux/generic/files/drivers/net/phy/ar8327.c b/target/linux/generic/files/drivers/net/phy/ar8327.c index 07e837e..96f3378 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8327.c +++ b/target/linux/generic/files/drivers/net/phy/ar8327.c @@ -621,6 +621,22 @@ static int ar8327_hw_init(struct ar8xxx_priv *priv) { int ret; + u32 led_val; + + if (chip_is_ar833x(priv)) { + led_val = ar8xxx_read(priv, AR8327_REG_LED_CTRL3); + /* + * no default LED pattern is set for PHY 1 on AR8334 + * this code might not work correctly on AR8335 + */ + led_val = (led_val & BITS(8, 6)) >> 8; + dev_info(&priv->phy->dev, "led_val = %x\n", led_val); + if (led_val) + priv->chip_subver = 7; + else + priv->chip_subver = 4; + dev_info(&priv->phy->dev, "Detected AR833%d\n", priv->chip_subver); + } priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL); if (!priv->chip_data) @@ -1206,7 +1222,7 @@ const struct ar8xxx_chip ar8337_chip = { .config_at_probe = true, .mii_lo_first = true, - .name = "Atheros AR8337", + .name = "Atheros AR833X", .ports = AR8327_NUM_PORTS, .vlans = AR8X16_MAX_VLANS, .swops = &ar8327_sw_ops,